1. Field of the Invention
The present invention relates to a Viterbi decoding art and a data recording/reproducing apparatus and method thereof using it and more particularly to a Viterbi decoder and operation method which are used for signal reproducing in a magnetic storage and others and to a recording/reproducing apparatus and method thereof using it.
2. Description of the Prior Art
Recently, to realize a highly reliable signal reproducing circuit accompanying high density recording in a magnetic storage, a signal reproducing circuit by the Viterbi decoding system using the relationship of reproduced signals as described in "Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel" (IEEE Transactions on communications, VOL. COM-34, May 1986, p.p. 454-461), Roger W. Wood and others has been used. The Viterbi decoding system is a system for decoding data on the basis of the sampled data which is a sampled reproduced signal and operates the amplitude difference between the sampled data at the sampling time of `n` and at the previous sampling time of `n-p` and compares the amplitude difference and the reference value. When the amplitude difference is more than the reference value and the detected polarity is inverted, the decoding system sets 1 and in other cases, it sets 0. The constitution and operation of the conventional Viterbi decoder will be explained hereunder with reference to FIGS. 9 and 10. FIG. 9 is a block diagram of the conventional Viterbi decoder. Numeral 1 indicates a sampling circuit, 51 a storage circuit, 52 a subtracter, 53 a selector, 54 and 55 comparators, 56 and 57 exclusive OR circuits (abbreviated to EOR), 58 a flip-flop (abbreviated to DFF), 59 a counter which can count up to a numerical value of k, 60 an address storage circuit, 61 and 62 selectors, and 63 a random access memory (abbreviated to RAM) having k storage regions.
The sampling circuit 1 converts a reproduced signal obtained from a magnetic storage medium to sampled data X(n) whenever the sampling clock HCLK is triggered (hereinafter, the sampled data at the sampling time of`n`is expressed by X(n)). The Viterbi decoder compares the amplitude difference between the sampled data X(n) and X(n-p) and the reference value and decodes the data depending on the comparison result. The storage circuit 51 stores the sampled data X(n-p) at the sampling time of `n-p` and the subtracter 52 subtracts X(n-p) from X(n) so as to obtain the amplitude difference. The comparators 54 and 55 compare the amplitude between the amplitude difference and reference value (.+-.Vth or 0). The comparator 54 outputs `High` when X(n)-X(n-p)&gt;Vth or X(n)-X(n-p)&gt;-Vth and the comparator 55 outputs `High` when X(n)-X(n-p)&gt;0. On the basis of this detected result, the EOR 56 makes the peak value updating signal P high under the following condition and updates various statuses. Condition 1: The output of the comparator 54 is `High` and the output of the comparator 55 is `Low`, that is, Vth&lt;X(n)-X(n-p) and X(n)-X(n-p)&lt;0.
Condition 2: The output of the comparator 54 is `Low` and the output of the comparator 55 is `High`, that is, -Vth&gt;X(n)-X(n-p) and X(n)-X(n-p)&gt;0.
The EOR 57 is a circuit for indicating that the direction of polarity to be detected is changed. When the output of the comparator 55 does not match the output of the DFF 58 which stores the polarity of X(n)-X(n-p), the output of the EOR 57 goes high. The counter 59 counts up from 0 to k sequentially whenever the sampling clock HCLK is triggered. When the count reaches k, the counter starts to count from 0 again. The address storage circuit 60 stores the numerical value of the counter 59 when the peak value updating signal P is changed from `High` to `Low`. The selector 61 generates an address of the RAM 63. When the peak value updating signal P is high, the selector 61 outputs the value of the address storage circuit 60 as an address of the RAM 63. When the peak value updating signal P is low, the selector 61 outputs the output of the counter 59 as an address of the RAM 63. The RAM 63 outputs the data of the specified address as decoded data and stores the data outputted from the selector 62. Therefore, when the peak value updating signal P is low, the data stored in the RAM 63 is outputted sequentially as decoded data according to an address generated by the counter 59. On the other hand, when the peak value updating signal P is high, the data of the RAM 63 at the address stored in the address storage circuit 60 is rewritten to the output value of the EOR 57 via the selector 62. When the decoded data is 1, the rewritten data is read from the RAM 63 without being rewritten again. When the decoded data is 0, it is rewritten again before being outputted as decoded data and 0 is stored.
For example, assuming that a reproduced signal as shown in FIG. 10 is inputted to the Viterbi decoder, the status of each circuit becomes as shown below. The reproduced signal is sampled at the leading edge of the sampling clock and converted to sampled data at the positions of .circle-solid. shown in the drawing. The positions where the peak value updating signal P goes high are indicated by .smallcircle. shown in the drawing and a value indicated by X(n-p) is stored in the storage circuit 51. The amplitude difference operated by the subtracter 52 is indicated by the length of an arrow shown in the drawing. This amplitude difference is detected by the comparators 54 and 55 and the peak value updating time is decided by the EOR 56. When the peak value updating signal P is high, the numerical value of the RAM 63 at the address stored in the address storage circuit 60 is set to 1 when the polarity of the operation result X(n)-X(n-p) is changed. In other cases, it is set to 0. According to this operation, when the polarity of X(n)-X(n-p) is changed as shown at the sampling time of 0, 2, or 4, 1 is detected. When the polarity of operation result is not changed as shown at the sampling time of 5 or 6 even when the peak value updating is executed, 0 is detected. By repeating this operation, the decoded data becomes highly reliable data in which there are few discrimination errors.
As mentioned above, the conventional Viterbi decoder is constituted so as to operate X(n)-X(n-p), compare the result with the reference value, and discriminate the data according to the comparison result and provides a highly reliable data discrimination circuit.
As mentioned above, the Viterbi decoder can reduce data discrimination errors and realize highly reliable signal reproducing. However, the Viterbi decoder of the prior art uses a detection formula of Vth&lt;X(n)-X(n-p) and X(n)-X(np)&lt;0 or -Vth&gt;X(n)-X(n-p) and X(n)-X(n-p)&gt;0, so that the Viterbi decoder operates X(n)-X(n-p), compares the operation result with the reference value, detects the comparison result, and updates X(n-p). The processing of operation, comparison, and updating includes an operation for X(n) which is the current input, so that it is necessary to complete the processing before the next sampled data is inputted, that is, within one cycle of operation clock. When the operation clock frequency is low, this operational limitation is not questionable because the circuit processing time is shorter than one cycle of operation clock. However, when the operation clock frequency is high, the circuit operation time is longer than the operation clock cycle and the processing cannot be completed within one cycle of operation clock. Therefore, it is difficult to realize a high speed operation by the conventional Viterbi decoder.